![]() I've explained one way that I am pretty sure you can still lock it up, and I suspect that you have found another. Or perhaps that the user-space application interface to the driver and the locking between processes is not quite correct, and you are able to lock it up. However, in my experience, the Altera JTAG software has bugs. but it does seem like hanging issue appears for others as well just trying to use the system console in a very basic way. I dont believe im doing anything that shouldnt be possible. Any other ideas on how to do this? or possibly pause the nios from checking that memory (in case there is an access contention)?Īttached is an updated qsys just incase you see something there i was hoping that the master_write_from_file would be the answer. no errors, just hang up.Īny ideas? I just need to be able to load up a bunch of commands to memory before this trigger occurs. Master_write_from_file $myMaster "c:/mydir/bitStream34.bin" 0x20000004 I can watch each loop output text, but the second that i run the Printf("\nTriggerVal is x\n",verifyTriggerSet) VerifyTriggerSet = (IORD_32DIRECT(TRIGGERBUFFER,0)) Printf("\nTriggerReg is x\n",TRIGGERBUFFER) ![]() While(IORD_32DIRECT(TRIGGERBUFFER,0) != triggerCaptureVal ) I implemented the jtag mm master, and i do believe that it encompasses all memory, but my original triggering problem still exists: when i use the master_write_from_file in system console, that seems to jam up the following nios code: Ill try adding the jtag to avalon mm master in there and report back Was hoping that i could write master 0 at addr x4 and then read the same data back at master 1 addr x20000004, but the memory content doesnt line up: I tried a quick test on the memory offsets in system console. Here's some notes on the JTAG-to-Avalon-MM master. Personally, I think its "easier" to understand what is going on if you explicitly add the JTAG-to-Avalon-MM master to your design and use it to access the same addresses as the NIOS II master. Its possible you can use that to read/write the memory map. I believe the NIOS II processor debug interface can also be used via SystemConsole, however, I have not used it. You can then use SystemConsole to access the memory map via that master. You can add that to the top-level design, and connect it just as you have done with the NIOS II processor. There is another component called the JTAG-to-Avalon-MM bridge. I suspect that if you write with the JTAG memory master to address 0, then read with the NIOS processor from address 2000_0000h (the base address of the memory as viewed by the NIOS II processor) you will see the same data. I believe im using the built-in avalon controller within the memory.īecause that "master" is hidden within the memory controller, it can only see the memory addresses (most likely starting with an address of 0). Ive attached a screen shot of my qsys and mem settings. Your memory map has only one set of addresses. spi_0_external_MISO (GPIOSPIGPIO), // spi_0_external.MISO Also, here is part of my top level code: just the mem pins and the instantiation
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